---------------------------------------------------------------------------------
  -- Design Name : work.UserPkg.GenAdd32 Test Bench
  -- File Name   : GenAdd32.vht
  -- Function    : work.UserPkg.GenAdd32 test bench
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.TBPkg.all;
use work.UserPkg.all;

entity ExMemStack32_1024_vhd_tst is
  -- this page is intentionally left blank
end ExMemStack32_1024_vhd_tst;

architecture ExMemStack32_1024_arch of ExMemStack32_1024_vhd_tst is
  -- constants
  -- signals
  signal clk      : std_logic;
  signal cl       : std_logic;
  signal v        : std_logic;
  signal push     : std_logic;
  signal pop      : std_logic;
  signal dataIn   : Word32;
  signal dataOut  : Word32;
begin
  
  Clock_inst : Clock port map (
    clk => clk
  );
  
  ExMemStack32_1024_inst : ExMemStack32_1024 port map (
    clk       => clk,
    cl        => cl,
    push      => push,
    pop       => pop,
    dataIn    => dataIn,
    stackV    => v,
    dataOut   => dataOut
  );
  
  init : process
  -- variable declarations
  begin
    -- code that executes only once
    wait;                                 -- stop running
  end process init;
  
  always : process
    -- optional sensitivity list
    -- (        )
    -- variable declarations
  begin
    -- code executes for every event on sensitivity list
    report "Testing...";
    wait for 3 * CLOCK_PERIOD / 4;
    
    for clkCount in 0 to 270 loop
      cl <= '0';
      case clkCount mod 270 is
        -- Test #1
        when 0 =>
          dataIn <= "00000000000000000000000000000100";
          push <= '1';
          pop <= '0';
        -- Test #2
        when 1 =>
          dataIn <= "00111111111111111111111111111111";
          push <= '1';
          pop <= '0';
        -- Test #3
        when 2 =>
          dataIn <= (others => '1');
          push <= '1';
          pop <= '0';
        -- Test #4
        when 3 =>
          dataIn <= "00000000000111111110000111111111";
          push <= '1';
          pop <= '0';
        -- Test #5
        when 4 =>
          dataIn <= "00000000000000000010000000000001";
          push <= '0';
          pop <= '1';
        -- Test #6
        when 5 =>
          dataIn <= "00000000000000000010000000000001";
          push <= '0';
          pop <= '1';
        -- Test #7
        when 6 =>
          dataIn <= "00000000000000000010000000000001";
          push <= '0';
          pop <= '1';
        -- Test #8
        when 7 =>
          dataIn <= "00000000000000000010000000000001";
          push <= '0';
          pop <= '1';
        -- Test #9
        when 8 =>
          dataIn <= "00000000000000000010000000000001";
          push <= '0';
          pop <= '1';
        -- Test #10-#1032
        when others =>
          dataIn <= (clkCount mod 32 => '1', others => '0');
          push <= '1';
          pop <= '0';
      end case;
      wait for 5 ps; -- da ne vrsio pretvaranja u momentu promene vrednosti na ulazu
      assert v = '0' report "    overflow" severity note;
      --report "    DataIn  = " & hstr(dataIn);
      report "    DataOut = " & hstr(dataOut);
      wait for CLOCK_PERIOD - 5 ps;
    end loop;
    
    assert false report "Testing done." severity failure;
    wait;                                 -- stop running
  end process always;
end ExMemStack32_1024_arch;

configuration ExMemStack32_1024_vhd_cfg of ExMemStack32_1024_vhd_tst is 
	for ExMemStack32_1024_arch
    -- this page is intentionally left blank too
	end for;
end ExMemStack32_1024_vhd_cfg;